CHA1077A rohs compliant ref. dsCHA1077A8266 - 22 oct 2008 1/6 specification s subject to change without notice united monolithic semiconductors s.a.s. route dpartementale 128 - b.p.46 - 91401 orsay cede x france tel. : +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 33 03 09 w-band low noise amplifier gaas monolithic microwave ic description the CHA1077A is a w-band monolithic 3- stages low noise amplifier. all the active devices are internally self-biased. this chip is compatible with automatic equipment for assembly. the circuit is manufactured on phemt process: 0.15m gate length, via holes through the substrate, air bridges and electron beam gate lithography. it is available in chip form. main features w-band low noise amplifier high gain wide operating frequency range high temperature range on-chip self biasing additional external resistor allows to choose getting more gain instead of a minimum noise factor automatic assembly oriented low dc power consumption bcb layer protection chip size: 2.6 x 1.32 x 0.1mm out in +v -v w-band amplifier block-diagram small signal gain main characteristics tamb = +25c symbol parameter min typ max unit f_op operating frequency 76 77 ghz g_lin small signal gain 15 db nf noise figure 4.5 db p_1db output power at 1db gain compression 9 dbm esd protections: electrostatic discharge sensitive device observe handling precautions !
CHA1077A w-band lna ref. dsCHA1077A8266 - 22 oct 2008 2/6 specification s subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 electrical characteristics full operating temperature range, used according to section typical assembly and bias configuration. symbol parameter min typ max unit f_op operating frequency 76 77 ghz g_lin small signal gain 11 15 19 db g_fl small signal gain flatness 0.5 1 db nf noise figure 4.5 6.5 db p_out_1db output power at 1db gain compression 6 9 dbm is reverse isolation 20 30 db vswr_in vswr at input port (50 w ) 2:1 2.5:1 vswr_out vswr at output port (50 w ) 2:1 2.5:1 +v positive supply voltage (1) 4.4 4.5 4.6 v +i positive supply current 40 70 ma -v negative supply voltage (1) -4.6 -4.5 -4.4 v -i negative supply current -10 -6 0 ma top operating temperature range -40 100 c (1) negative supply voltage must be applied at leas t 1us before positive supply voltage. absolute maximum ratings (1) symbol parameter values unit p_in maximum input power (2) 3 dbm +v positive supply voltage 5 v -v negative supply voltage -5 v +i positive supply current 80 ma -i negative supply current -13 ma tstg storage temperature range -55 to +155 c (1) operation of this device above anyone of these parameters may cause permanent damage. (2) cw mode
w-band lna CHA1077A ref. dsCHA1077A8266 - 22 oct 2008 3/6 specification s subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 chip mechanical data and pin references unit = m external chip size (layout size + dicing streets) = 2600x1320 +/-35 chip thickness = 100 +/- 10 hf pads (5,8) = 105 x 86 (bcb opening) dc/if pads = 86 x 83 (bcb opening) pin number pin name description 4, 6, 7, 9 ground: should not be bonded. if required, please a sk for more information. 3 ground (optional) 5 out rf output port 8 in rf input port 0 +v positive supply voltage 1 -v1 negative supply voltage for the first stage 2 -v23 negative supply voltage for the second and third st age origin 0,0 layout 2530x1250 405 55 7 8 9 6 5 4 70 2475 405 1 945 0 645 2 1245 3 1845 10991
CHA1077A w-band lna ref. dsCHA1077A8266 - 22 oct 2008 4/6 specification s subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical assembly and bias configuration to get mini mum noise figure this drawing shows an example of assembly and bias configuration. all the transistors are internally self-biased. an external capacitor is recommended for the positive and negative supply voltages. for the rf pads the equivalent wire bonding inducta nce (diameter=25m) have to be according to the following recommendation. port equivalent inductance (nh) wire length (mm) (1) in l_in = 0.25 0.34 out l_out = 0.25 0.34 (1) this value is the total length including the ne cessary loop from pad to pad. for a micro-strip configuration a hole in the subst rate is necessary for chip assembly. dc lines +v >= 120pf l_in - strip line l_out - strip line 7 8 9 6 5 4 0 2 3 -v 10991
w-band lna CHA1077A ref. dsCHA1077A8266 - 22 oct 2008 5/6 specification s subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical assembly and bias configuration to increase the gain lets tune the value of the external resistor r to control the biasing point of the first stage and then getting a higher gain for the lna (trade-o ff ability between the gain and the noise factor). typical value of the external resistor r r (k w ww w ) description 0 low-noise configuration 2 maximum gain configuration r dc lines +v >= 120pf l_in - strip line l_out - strip line 7 8 9 6 5 4 1 0 2 -v 10991
CHA1077A w-band lna ref. dsCHA1077A8266 - 22 oct 2008 6/6 specification s subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 as the connections at 77ghz (between mmic and mmic or between mmic and external substrate) are critical, the transition matching network is sp lit into two parts: one on mmic and one on the external substrate. this choice allows doing also a direct connection between mmics. for a connection to an external substrate a network is pr oposed on soft substrate for in and out ports. the following drawings give the dimensions for a ro 3003 substrate (thickness=0.127mm, e r=3). proposed matching network for a 50 w transition between in port and a -strip line on r o3003 substrate. proposed matching network for a 50 w transition between out port and a -strip line on ro3003 substrate. ordering information chip form : CHA1077A98f/00 information furnished is believed to be accurate an d reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by impli cation or otherwise under any patent or patent rights of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and re places all information previously supplied. united monolithic semiconductors s.a.s. products are not authorized for use as critical components in life support devices or s ystems without express written approval from united monolithic semiconductors s.a.s. wire length : 340 m 100 um 300 um 370 um 500 um 235 um 225 um bonding area 225 um 865 um 300 um 500 um 235 um bonding area wire length : 340 m
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